The present invention is directed to a bipolar transistor on a SOI substrate and to an appertaining manufacturing method.
A CBiCMOS process serves the purpose of simultaneously manufacturing the following, active components: npn bipolar transistors, pnp bipolar transistors, n-MOS transistors and p-MOS transistors. The realization of a complementary BiCMOS process (CBiCMOS) is of great technical and economic interest when the two following demands are met. First, the CBiCMOS process can be significantly more complex, i.e. more complicated than the pure CMOS process. Second, the components must have extremely good function properties (performance).
The bipolar transistors are vertically constructed in a realization of the four different transistor types on a normal substrate of bulk silicon or, respectively, on thick SOI substrates (useful silicon layer, what is referred to as the body silicon, thicker than 1 .mu.m). The process outlay, however, is extremely high given the desired degree of performance. A CBiCMOS process can be realized far more simply on thin SOI substrates having a body silicon layer with a thickness of less than 0.2 .mu.m. In all known methods, the bipolar transistors, like the MOSFETs, are laterally constructed. The structural format of the two transistor types is extremely similar and the complexity of the manufacturing method is relatively low. Such a process concept is described, for example, in the publication by S. Parke, et al., "A Versatile, SOI BiCMOS Technology with Complementary Lateral BJT's", in IEDM 92, 453-456 (1992). There are also concepts for a complementary bipolar process on a thin body silicon, such as disclosed in, for example, R. Dekker et al. in IEDM 93, 75-78 (1993), that can be expanded to a complete CBiCMOS process. In contrast to the vertical structure, a lateral structure of the bipolar transistors has a few fundamental disadvantages that drastically deteriorate the function properties. The electrical connection of the relatively narrow base region between emitter and collector can only ensue via the long transistor sides, resulting in a high base resistance. For an acceptable base resistance, the transistors must be implemented with short emitter lengths and must be connected in parallel. This increases the area requirement. The current yield of these embodiments is extremely low because of the small effective emitter areas of the latter transistors. For an acceptable current, there is again the necessity of connecting a plurality of transistors in parallel, which also substantially increases the area requirements. When a polysilicon emitter is eliminated because of the compatibility with the CMOS process in order to keep the outlay low, setting the gain of the transistors is made more difficult because of the elimination of the polyemitter effect.